Computer graphics display systems are commonly used for displaying graphical representations of objects on a two-dimensional video display screen. Current computer graphics display systems provide highly detailed representations and are used in a variety of applications. A computer graphics display system generally comprises a central processing unit (CPU), system memory, a graphics machine and a video display screen.
In typical computer graphics display systems, an object to be presented on the display screen is broken down into graphics primitives. Primitives are basic components of a graphics display and may include points, lines, vectors and polygons (e.g., triangles and quadrilaterals). Typically, a hardware/software scheme is implemented to render, or draw, the graphics primitives that represent a view of one or more objects being represented on the display screen.
Generally, the primitives of the three-dimensional object to be rendered are defined by the host CPU in terms of primitive data. For example, when the primitive is a triangle, the host computer defines the primitive in terms of the X, Y and Z coordinates of each of its three vertices, the normals of the vertices, N.sub.x, N.sub.y and N.sub.z, and the red, green, blue and alpha (R, G, B and .alpha.) color values of each vertex. Alpha is a transparency value. Rendering hardware interpolates all of this data to compute the display screen pixels that represent each primitive, and the R, G, B and .alpha. values for each pixel.
Additionally, the primitives may also be defined in terms of texture by using texture mapping when rendering images. Texture mapping allows different parts of an object being rendered to have different appearances, such as when it is necessary or desirable to render an object which is comprised of several composite features, such as a brick wall comprised of several bricks. Rather than drawing each brick individually, a wall can be drawn and then a brick wall texture can be mapped onto the wall. Texture coordinates are usually referred to as the s, t, r and q coordinates in computer graphics display systems.
A typical graphics machine of a computer graphics display system includes a geometry accelerator, a rasterizer, a frame buffer controller and a frame buffer. Texture mapping occurs in the rasterizer, which performs pixel rasterization and texel rasterization to render a texture-mapped image on the display. The geometry accelerator receives three-dimensional vertex data from the host CPU in terms of red, green, blue and alpha (R, G, B and a) data, X Y, and Z data, N.sub.x, N.sub.y and N.sub.z data, and s, t, r and q data for each primitive received by the geometry accelerator. The X, Y and Z coordinates define the locations of the vertices of the primitives on the display screen whereas the N.sub.x, N.sub.y and N.sub.z data define the directions of the normals of the vertices of the primitives. The geometry accelerator processes all this data and outputs new R, G and B data for each vertex to the rasterizer. Once the rasterizer receives the R, G, B data and the s, t, r and q data for the vertices, the rasterizer performs texture mapping and rasterizes the texture-mapped image. When the image to be rendered is two-dimensional, the information defining the image can be sent directly to the rasterizer without first being sent to the geometry accelerator.
Rasterizers capable of performing texture mapping generally comprise a texel rasterizing component and a pixel rasterizing component. These two components operate in parallel and are synchronized such that, as the pixel rasterizing component determines the location of a pixel on the screen, the texel rasterizing component determines the texture to be assigned to the particular pixel and outputs it to the pixel rasterizing component which maps it onto the particular pixel. For example, as the pixel rasterizing component determines the location of a pixel on the screen corresponding to a corner of a floor being rendered, the texel rasterizing component may determine the texture of a carpet to be mapped onto the pixel.
Within the texel rasterizing component, texture information and commands are received from the host CPU and processed to generate a texel which is output to the pixel rasterizing component. A front end component receives information sent to the texel rasterizer and decodes the information into information suitable for use by the texel rasterizer. The decoded information is then sent to various components in the texel rasterizer. The information is in the form of register commands and register data and object commands and object data. Generally, four different types of commands are issued by the front end component. These commands include register write commands, register read commands, object write commands and object read commands. These commands are issued on the unbuffered path, which is a bus having a width of a certain number of bits.
Of these commands, the register read command, the register write command and the object write commands are immediate mode commands. Immediate mode commands are those which take a fixed, or predetermined, amount of time from the time that the command is issued to the time the command has been completed. The immediate mode commands can be pipelined to increase performance since the amount of time required to issue and execute a command is known. Pipelining involves issuing new commands before data corresponding to commands previously issued has been returned to the command issuer. Since with immediate mode commands the duration of the command cycle is known, pipelining can be utilized because the front end knows which command corresponds to the returned data.
The object read command, however, is a variable mode command in that the amount of time from the time the command is issued to the time the data is read from cache and returned to the front end component is variable, or indeterminate. Generally, this object read cycle has a duration of approximately 40 states, although the exact duration is not known. One known solution to the variable mode problem is for the front end component to issue an object read command and wait until the data associated with the command has been returned to the front end component before issuing the next object read command. One major disadvantage to this method is that the latency from the time each object command is issued to the time the data returns back to the front end is approximately 40 states and currently object prefetching and pipelining are not being used to reduce this latency. Prefetching involves issuing several commands in advance even though many of these commands may not be executed and will later be discarded. Generally, prefetching is not implemented for immediate mode commands because it is unnecessary to use prefetching since those commands are issued and completed very quickly.
Another known solution to this variable mode problem is to use separate buses for the variable mode and immediate mode commands and data. By using two separate buses, pipelining has been implemented for the immediate mode commands and data, while prefetching and pipelining have been used for the variable mode commands and data. A disadvantage to using two separate buses is that the two buses and their associated logic circuits take up a large amount of space and increase costs. The bus for handling the variable mode commands and data may be, for example, forty bits wide whereas the bus for handling the immediate mode commands and data may be, for example, 70 bits wide. Therefore, a separate bus for the variable mode protocol would require an additional 40 lines.
Accordingly, a need exists for a method and apparatus which allows the variable mode commands and data and the immediate mode commands and data to be handled by a single bus while also increasing object read back performance by pipelining immediate and variable mode commands while also prefetching object read commands.